1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus and a bit line equalizing circuit.
2. Related Art
In general, a semiconductor memory apparatus includes a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines. The bit line structure of the semiconductor memory apparatus may include a folded bit-line structure and an open bit-line structure. In particular, the open bit-line structure has been proposed to achieve a high integration of the semiconductor memory device.
In the folded bit-line structure, a bit line and a bit line bar are provided in a same cell mat. In the open bit-line structure, however, a bit line and a bit line bar exist in different cell mats.
FIG. 1 illustrates a conventional semiconductor memory apparatus having an open bit-line structure.
Referring to FIG. 1, the semiconductor memory apparatus having an open bit-line structure includes unit memory cell arrays CA0 to CAx and bit-line sense amplifier units BS0 to BSx+1 which are alternately arranged.
Each of the unit memory cell arrays CA0 to CAx includes a plurality of memory cells coupled between a plurality of word lines WL0 to WLm and a plurality of bit lines BL0 to BLn.
Furthermore, each of the bit-line sense amplifier units BS0 to BSx+1 is commonly coupled to bit lines BL0/BLB0 to BLn/BLBn coupled to two unit memory cell arrays adjacent to each other.
Accordingly, when a specific word line is selected and a bit is line crossing the selected word line is enabled, a bit line sense amplifier BLSA amplifies and outputs data stored in a corresponding memory cell according to a potential difference between the bit line coupled to the corresponding memory cell and a bit line bar existing in an adjacent cell mat.
In the semiconductor memory apparatus having an open bit-line structure, a bit line sense amplifier unit treats a bit line BL and a bit line bar BLB, which exist in different cell arrays, as one pair of bit lines when sensing data.
A designated number of unit memory cell arrays may be assumed to be one bank. In this case, the bit-line sense amplifier units BS0 and BSx+1 positioned at both edges of the bank are coupled to the bit lines or bit line bars of the memory cell arrays CA0 and CAx, respectively. However, bit line bars or bit lines forming one pair do not exist. Accordingly, sacrifice memory cell arrays PCA0 and PCA1 may be disposed at both edges of the bank such that the bit-line sense amplifier units BS0 and BSx+1 positioned at both edges of the bank perform a sensing operation.
FIG. 2 is a diagram explaining the operation of a bit-line sense amplifier in a general open bit-line structure.
FIG. 2 illustrates the bit-line sense amplifier BLSA disposed at one edge between both edges of the bank and the sacrifice memory cell array PCA0 and the unit memory cell array CA0 which are coupled to the bit-line sense amplifier BLSA.
The sacrifice memory cell array PCA0 includes a plurality of memory cells coupled between the plurality of word lines WL0 to WLm and the plurality of bit lines BL0 to BLBn, like the unit memory cell array CA0 which is a main memory cell array.
The bit-line sense amplifier BLSA includes an equalizing circuit 122 and an amplification circuit 124. The equalizing circuit 122 is configured to precharge or equalize a bit line BL and a bit line bar BLB to a predetermined potential. The amplification circuit 124 is configured to sense and amplify the potential difference between the bit line BL and the bit line bar BLB.
The equalizing circuit 122 includes first and second precharge elements T_PCG1 and T_PCG2 and an equalizing element T_EQ. The first and second precharge elements T_PCG1 and T_PCG2 are configured to precharge the bit line BL and the bit line bar BLB to a precharge voltage VBLP in response to a bit line equalize signal BLEQ. The equalizing element T_EQ is configured to equalize the bit line BL and the bit line bar BLB to the precharge voltage VBLP in response to the bit line equalize signal BLEQ.
The amplification circuit 124 may be configured in a latch type coupled between the bit line pair BL/BLB, and amplifies the voltage level of the bit line pair BL/BLB using sense amplifier power signals RTO and SB outputted from a bit-line sense amplifier control circuit as a power supply source.
During the sensing operation, a parasitic capacitance component 22 exists in the memory cell array CA0. Since the sacrifice memory cell array PCA0 has the same structure as the memory cell array, a parasitic capacitance component 24 having the same value as the parasitic capacitance component 22 of the memory cell array CA0 also exists in the sacrifice memory cell array PCA0.
Accordingly, the parasitic capacitance components having the same value exist in the bit line pair BL/BLB coupled to the bit line sense amplifier BLSA such that the data of the memory cell is accurately sensed.
FIG. 3 is a timing diagram explaining the sensing operation of the semiconductor memory apparatus of FIG. 2.
When the bit line BL and the bit line bar BLB are charged to a low level and a high level, respectively, the precharge signal PCG is inputted, and the bit line equalize signal BLEQ is enabled. Accordingly, the first and second precharge elements T_PCG1 and T_PCG2 and the equalize element T_EQ are turned on, and the bit line pair BL/BLB is gradually charged to the same level, that is, a precharge voltage.
In FIG. 3, a time required until the bit line pair BL/BLB is precharged after the precharge signal PCG and the bit line equalize signal BLEQ are enabled may be represented by tA, and a time required until the bit line equalize signal BLEQ is disabled after a word line active signal ACT is enabled may be represented by tB. In this case, a RAS (row address strobe) precharge time tRP expressed as tA-tB should satisfy a designated time range. The RAS precharge time refers to a time required until the bit line pair BL/BLB is charged to the same precharge voltage after the precharge signal PCG is is enabled.
For this operation, the bit line BL and the bit line bar BLB should reach the precharge voltage at the same time. In the semiconductor memory apparatus of FIG. 2, the memory cell array CA0 and the sacrifice memory cell array PCA0 have the same structure. Therefore, since the capacitances of the bit line pair are accurately matched, it is impossible to satisfy a required RAS precharge time tRP.
However, the sacrifice memory cell arrays PCA0 and PCA1 are simply used to adjust the bit line capacitance in the bit line sense amplifier BLSA, but are not used to store data or the like. Therefore, the sacrifice memory cell arrays PCA0 and PCA1 may decrease the net die.
In order to solve such a problem, the following method has been proposed: capacitors using a storage node are formed at both edges of the bank instead of the sacrifice memory cell arrays and used to match the capacitances of the bit line pair.
FIG. 4 illustrates a bit-line capacitance matching circuit.
The bit-line capacitance matching circuit of FIG. 4 is coupled to the bit line sense amplifiers disposed at both edges of the bank.
That is, the bit line sense amplifiers disposed at both edges of the band should be coupled to a bit line and a bit line bar. When one of the bit line pair is a bit line or bit line bar extended from a memory cell array, the bit line capacitance matching circuit of FIG. 4 is formed in a bit line bar or bit line which is paired with the bit line or bit line bar.
Such a bit line capacitance matching circuit may be configured by using a storage node which is formed when a unit memory cell is formed.
When the capacitance matching circuit of FIG. 4 is configured to replace the sacrifice memory cell array PCA0 of FIG. 2, a positive capacitance corresponding to the bit line capacitance component 22 of the memory cell array CA0 is compensated by the capacitance matching circuit of FIG. 4.
However, a unit capacitance formed by using a storage node has a larger storage capacity than the unit capacity of a parasitic capacitance, and should use a plurality of capacitors C1 to Ci having a large capacity. Therefore, there is a limitation in matching the capacitances of the bit line pair. Furthermore, since the process is unstable during an initial process set-up, there are difficulties in adjusting a target capacitance value.
FIG. 5 is a timing diagram explaining a sensing operation of a semiconductor memory apparatus to which the bit line capacitance matching circuit of FIG. 4 is applied.
In a state where the bit line BL and the bit line bar BLB are charged to a low level and a high level, respectively, the precharge signal PCG is inputted and the bit line equalize signal BLEQ is enabled. Accordingly, the first and second precharge elements T_PCG1 and T_PCG2 and the equalize element T_EQ are turned on, and the bit line pair BL/BLB is gradually charged to the same level, that is, the precharge voltage.
However, although the capacitors having the same value as the bit lines forming a pair are inserted into the bit line capacitance matching circuit based on the calculated value, there may occur a capacitance difference between the bit line pair because the capacitors composing the capacitance matching circuit are formed by using the storage node.
As a result, the time required for equalizing the bit line pair to the same level may differ due to the capacitance mismatch between the bit line pair (refer to A or B of FIG. 5).
Accordingly, compared with the timing diagram of FIG. 3, the time required for equalizing the bit line pair increases by ΔT. This means that the time to required until the bit line pair reaches the precharge voltage VBLP after the precharge signal is enabled increases by ΔT. Furthermore, since the RAS precharge time tRP should be further secured by ΔT, the operation time of the semiconductor memory apparatus inevitably increases.